1. Field of the Invention
Embodiments of the invention relate generally to semiconductor devices, and host devices incorporating same. More particularly, embodiments of the invention relate to a tape automated bonding (TAB) packages adapted to flexibly connect a host device element, such as a glass panel.
2. Description of the Related Art
The computational and data manipulation circuitry of semiconductor devices is implemented on small dies formed on portions of a silicon wafer. In and of themselves, semiconductor dies are very small and quite fragile. That is, in their native “cut-from-the-wafer” state, semiconductor dies—while fully functional in their circuitry—are not very useful since their fragile nature prevents practical integration within a host device, and their small size precludes most conventional connections to their internal circuitry. Thus, the need for effective semiconductor packaging techniques arises. The terms “package” or “packaging” in this context refer to any material or technique adapted to provide physical protection and/or electrical connection to/from a semiconductor die.
Semiconductor devices, such as microelectronic devices, memory devices, etc., typically encase their constituent semiconductor die in a package or housing in order to provide the die with protection from mechanical shock and/or the corrosive effects of the surrounding environment. Semiconductor die packages come in a variety of form factors and types. One common package encases the semiconductor die between a base and a cover. Another common package encapsulates the semiconductor die in a plastic or resin compound.
Electrical connection to the Input/Output (I/O) pads of a semiconductor die is commonly provided by a leadframe. Here again, leadframes come in many different form factors, but generally provide electrical connection between a variety of external circuits and the I/O pads of a semiconductor die through the packaging materials. A leadframe may be connected to a semiconductor die using one of several conventional techniques. Two conventional techniques adapted to the connection of a leadframe with respective I/O pads on a semiconductor device involve the respective use of thin wire bonds or an interconnect tape.
Techniques using an interconnect tape are commonly referred to as “tape automated bonding (TAB)”. In TAB, electrical connections (e.g., connections to power lines, and/or signal lines, etc.) are patterned onto the interconnect tape. During an interconnection process, a semiconductor die is positioned over the tape such that bonding sites (e.g., leads or pads formed on the semiconductor die) are aligned with respective interconnections on the tape. The semiconductor die is then bonded in place using metal bumps or solder balls, for example.
Once connection is properly established between bonding pads on the semiconductor die and the interconnect tape, the semiconductor die is able to make use of a connection pattern formed on the tape. This connection pattern most typically takes the form of a plurality of thin metal leads. Each one of the plurality of leads includes an “inner lead” or “inner lead portion.” The very fine and somewhat fragile nature of the inner leads preclude their direct use as electrical connections to external circuits. Thus, as each respective inner lead extends outward from the semiconductor die it migrates in form to a more robust (e.g., thicker and stronger) structure termed an “outer lead” or “outer lead portion.” Outer lead portions are adapted to be bonded to a leadframe, a circuit board, an external circuit connection, or a signal line, etc. Thus, an individual lead typically comprises an inner lead portion connected to a bonding pad on the semiconductor die and an outer lead portion bonded to a leadframe, a printed circuit board, an external circuit connection, or a signal line, etc.
The flexible interconnect tape used in TAB processes comes in several different types; for example, a single layer type having an all metal (or metalized) construction, a two layer type having a metal layer supported on a dielectric backing layer (e.g. a base film), or a three layer type having metal layer bonded by an adhesive layer to a dielectric layer. In TAB interconnect tape types incorporating a dielectric, the dielectric is typically formed from a polymide of about 2 to 5 mils in thickness. In contrast, the metal layer is usually formed from a highly conductive material such as copper or a dilute copper alloy and has a typical thickness ranging from 0.5 to 6 mils. Standard size interconnect tapes have widths of, for example, 35 mm, 45 mm and 70 mm, and thicknesses ranging from about 50 to 100 microns.
Leads may be formed from the metal layer of an interconnect tape using conventional photolithography processes. Lead portion widths as thin as 2 mils are commonly fabricated.
TAB provides several advantages over wire bonding techniques. These advantages include: smaller bonding pad structures and a finer bonding pitch, reduced use of gold, a smaller bond geometry, increased production rates, and stronger, more uniform inner lead bonding. TAB produced devices are physically flexible and facilitate multi-chip module manufacturing.
Thus, TAB is often a better production alternative over wire bonding techniques for applications within host devices requiring very fine bond pitches, reduced die size, and higher semiconductor device densities. TAB is also the fabrication technique of choice for semiconductor devices that routinely experience physical motion or stress (e.g., bending, torque, compressive or tensile stressing, etc.) in their use within a host device. A requirement for reliable use under physical motion or stress is often placed on some semiconductor devices used, for example, within LCD panels, printers, folding gadgets like cell phones, laptops, PDAs, etc.
However, the incorporation of a TAB fabricated semiconductor device within host devices poses many challenges. Consider, for example, the difficulties inherent in the incorporation a TAB package, such as a tape carrier package (TCP) or a Chip-On-Film package (COF) within host devices such as laptop computers, PDAs, cell phones, GPS devices, digital video cameras, etc.
Conventional COF packages and TCPs differ in several aspects. For example, TCPs are often formed with a window cut-out in the tape to allow backside visibility and access to a mounted semiconductor die, whereas COF packages typically omit the window. The interconnect tape used in COF packages generally tends to be thicker than the interconnect tape used in TCPs. In the description that follows, the term “TAB package” generally refers to any semiconductor package formed using a TAB process, and specifically includes at least TCP and COF package types.
TCP and COF packages are frequently used as Liquid Crystal Display (LCD) drivers (termed LDIs) in certain host devices. Indeed, LDIs implemented using a TCP or a COF package are often used to physically bridge LCD arrays with a separate printed circuit board (PCB) comprising a driver, controller or similar computational/data manipulation hardware. The use of flexible semiconductor packaging and connections techniques to implement (or facilitate the implementation of) moveable joints between elements of a host device has enabled many new consumer products that are compact, elegant and versatile.
However, these developments have placed increasing importance on the long-term reliability of TAB packages used in such applications. Several problems associated with the use of a TAB package as a flexible connection between host device elements will be described in relation to a selected example. This example involves the connection of a glass panel, such as those commonly used in LCD displays, with another host device element, such as a PCB containing a driver circuit or controller. This example is illustrated collectively in Figures (FIGS.) 1A through 1C and FIG. 2.
FIG. 2 is a cross-sectional view showing a glass panel 2 connected to one end of a TAB package 5. Glass panel 2 generally comprises a cover portion 2a and a connection portion 2b having a beveled edge 8. A connection pattern 3 formed on glass panel portion 2b is electrically connected to a connection pattern 6 formed on TAB package 5 via an anisotropic conductive film (ACF) 4. The use of ACF in this regard is well understood. In the illustrated example, both connection patterns (3 and 6) are implemented as a plurality of parallel leads.
Related FIGS. 1A, 1B, and 1C further illustrate the problems commonly attendant to the foregoing arrangement. By design, TAB package 5 is intended to facilitate a folding motion (e.g., bending) in the direction indicated by arrow 9 over beveled edge 8 for the other host device element (not shown) connected to the other end of TAB package circuit 5. This folding motion places stress on the outer lead portions 6a of connection pattern 6. This stress tends to concentrate in a region of connection pattern 6 between the ACF 4 bonded outer lead portions 6a and the solder resist 7 reinforced portion of connection pattern 6, (e.g., the terminal portions of the plurality of leads). As indicated in FIGS. 1B and 1C, the connection pattern portions within this stressed region are more prone to cracking. Potential cracking of the outer lead portions is an obvious negative and will dramatically impact the overall reliability of the host device incorporating the TAB package connecting the glass panel. Over time, however, repeated motion between the host device elements flexibly connected by the TAB package may result in exactly this negative outcome.